One type of integrated circuit which has been recently developed comprises a thin layer of single crystalline silicon extending over and insulated from the surface of a silicon substrate. This type of integrated circuit is called a "SIMOX" device. Circuit are formed in the thin layer of silicon by forming various electrical components, such as transistors, in the thin layer. One method of making a SIMOX device is to implant oxygen ions into the surface of a substrate of single crystalline silicon so that the oxygen ions are spaced from the surface of the substrate. The substrate is then heated so that the oxygen ions react with the silicon and form a thin layer of silicon dioxide beneath the surface of the substrate with a thin layer of the silicon extending over the oxide layer.
CMOS circuits formed in a SIMOX device which has fully depleted NMOS and PMOS transistors having relatively low breakdown voltages when the transistors are operated in the "floating body" mode. Connecting the body to the source of the transistors substantially increased the breakdown voltage. When an NMOS transistor is used as an ESD protection structure, it is normal to connect the gate of the NMOS to the source. This is often referred to as a grounded-gate NMOS, or ggNMOS. The structure actually providing the ESD protection is the parasitic bipolar NPN transistor inherently formed by the NMOS transistor. The gate of the NMOS transistor merely serves to determine the emitter-collector spacing, and to a small extent, to control the trigger voltage. Once impact ionization occurs at the base-collector junction, avalanche multiplication results in the sudden reduction in collector-emitter voltage to a substantially lower level than the initial breakdown voltage. This phenomenon is sometimes referred to as snap-back.
Premature failure of a protection structure can occur in devices with large differences between the trigger and snap-back voltages if one section (of a multi-section) of the protection structure turns on first. This is because the voltage across the terminals drops to the snap-back holding voltage, and the "on" segment passes all of the current, preventing the voltage across the other sections reaching the required snap-back trigger voltage. It is common practice to add resistance in series with each segment, so that if one section "fires" the voltage drop across an "on" segment, plus the voltage across the series resistor, will allow the other segments to achieve the required trigger voltage. However, if the difference between the trigger and snap-back voltages is large, this approach requires an undesirably high series resistance. The ideal ESD protection structure would have virtually no leakage current prior to the trigger voltage, and almost no difference between the trigger and snap-back voltages.
During the development of a 0.35 micron SIMOX ESD protection device, it was found that ggNMOS devices with a floating body had virtually identical trigger and snap-back voltages, but relatively high leakages. Also, process spreads sometimes resulted in the snap-back holding voltage being below the maximum supply voltage used during burn-in of the product. Clearly, this was an undesirable situation. Connecting the body of the device to the source and gate eliminated the leakage problem, but doubled the trigger voltage while not affecting the snap-back voltage. A longer gate length (wider NPN base) did not substantially alter the device characteristics. Therefore, a modification of the structure was necessary to achieve the desired ESD protection characteristics.